1. Field of the Invention
The present invention relates to a system, method, and apparatus to implement low power high performance transceivers with scalable analog to digital conversion resolution and dynamic range.
2. General Background
A typical communications receiver operates in multiple modes wherein several different criteria of performance are suitable for each of the modes. For example, in a wireless LAN transceiver, it is desirable to have as little power consumption as possible during the time intervals that the receiver is scanning for a signal of interest (a.k.a. scanning mode, hereafter the search mode). The reason for this is that the transceiver can stay in the search mode for extensive time intervals. On the other hand, during the reception of a signal of interest (a.k.a. reception mode), a major criterion of performance is the capability of the receiver to process signals with high precision and sensitivity. The multiple operational modes, when viewed from the perspective of precision of A/D conversion, can be seen as contradictory.
Previously, receiver design involved a tradeoff between power consumption in the idle mode and the signal precision when receiving a signal of interest. However, this leads to a solution that is a compromise between the two conflicting performance requirements. As a result, sub-optimum performance is obtained in each of the operating scenarios. Furthermore, typical techniques of ADC dynamic range control have used high supply voltages and have depended on increases in the quality of the silicon process to improve the sensitivity of an A/D converter.
In conventional receiver front-end design, as shown in FIG. 1, a variable gain amplifier can precede the ADC. The Signal Power at the output of the ADC is measured and used to generate a control signal that is used to adjust the gain of the amplifier. The purpose of the loop shown in FIG. 1 is to insure efficient utilization of the ADC dynamic range.
Several problems can be attributed to the AGC Loop of FIG. 1. First, it requires a multiple bit Digital-to Analog converter (DAC) in the feedback path to control the variable amplifier gain. That normally contributes substantially to the cost of the receiver. Second, the variable gain amplifier usually exhibits gain response non-linearities that must be compensated for in the feedback path using look-up table (LUT) technique. Such techniques require a prior measurement of the variable gain amplifier non-linearities in order to generate the LUT. Furthermore, the characteristics of the amplifier will very likely change with temperature and with aging. Third, typically, the AGC amplifier is included in the design of receiver analog front-end, while the ADC, DAC and loop filters are implemented in the receiver digital back-end. This causes complexity in defining the interface between the two sections of the receiver typically done by two design teams.